Cadence Design Systems Reveals 3rd Gen 112G-LR PAM4 SerDes IP Under TSM's 5-NM Technology for Hyper-Scale Data Centers

Cadence Design Systems Inc CDNS showcased its third-generation 112G long-reach (112G-LR) SerDes IP on Taiwan Semiconductor Manufacturing Co Ltd’s TSM 5-nm process for hyper-scale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, and switch fabric systems on chip (SoCs) for next-generation cloud data centers.
The Cadence 112G-LR PAM4 SerDes IP on TSMC’s N5 process offers 25% power savings, 40% area reduction, and better design margins than second-generation architecture.
The 112G-LR SerDes solution on TSMC’s N5 process further solidifies Cadence’s leadership position with high-performance connectivity IP offerings for hyper-scale data centers. Customers can also enjoy the benefits associated with the TSMC N5 process technology, Cadence VP Sanjive Agarwala said.
Price action: CDNS shares traded higher by 2.88% at $127.01, and TSM shares traded higher by 1.94% at $114.02 on the last check Monday.

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